1. Field of the Invention
This invention generally relates to complementary metal/oxide/semiconductor (CMOS) imaging sensors and, more particularly, to a structure and associated fabrication process for using high energy ion implanting to form pixel diode sets and a well liner to isolate the photodiode sets in an array of photodiode sets.
2. Description of the Related Art
Silicon has characteristic photon absorption lengths that vary with the energy of the photons absorbed. For the wavelengths of 450 nanometers (nm), 550 nm, and 650 nm, the absorption lengths are 0.24 microns (μm), 1.13 μm, and 3.17 μm, respectively. This variation provides an opportunity to fabricate stacked diode junctions at depths that are capable of separating photons of various wavelengths, using standard CMOS manufacturing processes. Various technologies have been applied to this idea over the past 30 years and full color imaging is available in the market place.
FIG. 1 is a partial cross-sectional view of a stacked set of photodiodes formed in a Si-on-insulator (SOI) substrate (prior art). The photodiode set 100 includes three stacked photodiodes 102, 104, and 106. The blue color sensing photodiode (102) is fabricated on a silicon layer, while the green and red color sensing photodiodes (104 and 106, respectively) are fabricated in the Si substrate. The photodiode set is controlled by a transistor set, which is represented in this figure by transistor 108.
FIG. 2 is a schematic drawing depicting a triple cathode photodiode imager (prior art). In U.S. Pat. Nos. 6,727,521, 6,960,757, and 5,965,875 Merrill et al. disclose a filterless color CMOS imager cell having an n1/p1/n2/p2/n3/p-substrate structure. The pixel consists of five (5) junctions. All the p-type layers are grounded. The n1/p1 interface forms a junction for blue (B) diode. The green (G) diode is formed by the parallel combination of the n2/p1 and n2/p2 junctions. The red (R) diode is formed by the parallel combination of the n3/p2 and n3-p-substrate junctions. The n2/p1 and n2/p2 diodes have a common cathode and the anodes are all grounded. The triple-well technology of U.S. Pat. No. 5,965,875 requires large isolation area inside each pixel area.
The n-type layers are detector layers to collect photo-generated carriers, while the p-type layers are reference layers and are connected to common ground potential. The blue sensitive detector layer (n) at the surface of the silicon substrate has a reference layer (p) below it, while the green and red sensitive detector layers (n) have reference layers (p) above and below them. The electrical connection to the green and red sensitive detector layers are via the n-type plug formation. The structure of U.S. Pat. No. 6,727,521 promises a smaller pixel area because the lateral isolation area for the n-type plugs is much smaller than the triple well structures. However, to precisely locate the n-type detector layers and to confine the absorption layers for the respective R, G, and B light absorption and charge collection, two silicon epitaxial layers are required in the disclosed structure.
In U.S. Pat. No. 7,132,724, Merrill discloses three structures using conduction band alignment to fabricate a complete-charge-transfer detector with R, G, and B light absorption layers located at appropriate depths in the silicon substrate. All three structures are fabricated on p+silicon, substrates, the junction between the R, G, B absorption layers and the reference layers are either p− to p+ junctions or n to p junctions. The location of the absorption layers (p− or n layer) in all three structures are controlled by the p-type reference layer formation by ion implantation. In order to fabricate the three disclosed devices on a p+ silicon substrate, the absorption layers (p− or n layer) must be formed by silicon epitaxial growth.
FIG. 3 is a partial cross-sectional view of device based upon the schematic of FIG. 2 (prior art). As in FIG. 2, the triple cathode device has an n/p/n/p/n/p layered structure with three p-layers connected to a common ground. The three n-layers are the cathodes for the blue, green, and red diodes, and are connected to their respective active pixel sensor (APS) circuits. One problem associated with this structure is its complicated process steps. Two silicon epitaxial (epi) processes and multiple ion implantations are needed. One epi layer is formed between the blue and green diode junctions, and another epi layer is formed between the green and red diode junctions. Additionally, there is no structure isolating the green and red diodes from the neighboring pixel set. This lack of isolation decreases the spatial resolution of the imager sensor.
FIG. 4 is a partial cross-sectional view of a triple cathode photodiode set with partial isolation (prior art). The p+ substrate prevents cross-talk between adjacent photodiode sets (not shown) through the underlying substrate. P doped regions 207 and 208 form a partial vertical wall. However, regions 201, 203, and 204, between 207 and 205, and between 208 and 205 are lightly p (p−) doped. This p/p−/p/p−/p/p−/p+(207-201-205-203-208-204-p+) structure forms electron channels in the p-areas (201,203, and 204). Therefore, photo electrons in one pixel can diffuse to neighboring pixel. That is, although the pn depletion layer thickness does not extend to adjacent pixels, the electron diffusion length in the p layers is long, permitting photo electrons to be collected by adjacent pixels.
Digital camera technology is based upon the conflicting goals of increasing the pixel count, decreasing the chip size, and improving the signal-to-noise ratio. Higher pixel counts and smaller chip sizes mean that unit sensor area (the diode area) must be made smaller. When light strikes the diode, the photo electrons are generated and collected to the cathode. The photo electrons generate the signal. Undesirably, the signal-to-noise ratio decreases with smaller diode sizes, if the noise remains constant. One way to increase the signal is to use the area outside the diode to collect the photo electrons at the cathode. Regions 201, 203 and 204 are areas that extend outside the photodiode (past regions 207 and 208) that can absorb photons. Photo electrons generated in regions 201, 203 and 204 diffuse into the diode and are collected by the cathodes. Therefore, the signal is improved (increased). However, as described above, regions 201, 203 and 204 can be an electron channel between adjacent pixels, and degrade resolution.
Double junction and triple junction photodiodes with shared or independent color pixel sensor outputs are another solution to the above-mentioned problems. The process steps for these devices are much simpler than the triple cathode structure shown in FIG. 3. The separation of the blue, green, and red signals is performed by the APS circuit, and these three signals are integrated and readout sequentially. Therefore, the use of an external mechanical shutter for “still” shot imaging remains a problem. Additionally, the pixel size is relatively large because of the isolation required between pixels in an array.
FIG. 5 is a partial cross-sectional view of a triple cathode structure, fabricated without the use of an n/p/n/p/n/p layered structure, as proposed by Gergel et al. (prior art). Photo-generated electrons are collected on the cathode by the long electron diffusion length in the lightly p-typed doped layer. The separation of the blue, green, and red photon-generated electrons is by the p+-p junction. Although BB—1 (Buried barrier) separates blue and green photon-generated electrons, and BB—2 separates green and red photon-generated electrons, there are no structures to completely prevent unintended electron flow through the substrate to neighboring red diode junctions.
It would be advantageous if a multi-junction photodiode color imager array could be fabricated with a minimum number of process steps, by eliminating the necessity of forming epitaxial Si layers.